
#Enabling BLI flops to help with timing closure. For latency and based on how the design is to be used these BLI registers can be disabled.
set_property BLI TRUE [get_cells {bank*_fabric2xphy_bli*[*]}]
set_property BLI TRUE [get_cells {bank*_phy2fabric_q_reg[*]}]

##########################################################################################
#Clocking Settings #######################################################################
#  We are using a single input clock to route through a BUFG to fanout to all of the banks
#  to reduce and manage the skews to each of the cores and the PLLs within the cores. As
#  the routing skews using traditional fabric routing is prohibitive, the clock routing
#  skews are preferable. As the following CLOCK_DEDICATED_ROUTE setting should be used
#  to prevent DRCs being flagged.
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_REGION [get_nets clk_bufg]

#  Given that we know where the clocks are being routed to this tutorial will use placement constraints for a consistent result.
#  Floorplanning and other methods can be used as long as the PLL's are reasonably placed and the clock routes are not negatively
#  impacting performances.
set_property LOC XPLL_S0X7Y0 [get_cells XPLL_banka_inst]
set_property LOC XPLL_S0X9Y0 [get_cells XPLL_bankb_inst]
set_property LOC XPLL_S0X13Y0 [get_cells XPLL_bankc_inst]
set_property LOC XPLL_S0X21Y0 [get_cells XPLL_bankd_inst]
set_property LOC XPLL_S0X23Y0 [get_cells XPLL_banke_inst]
set_property LOC XPLL_S0X19Y0 [get_cells XPLL_bankf_inst]


create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]

#Capture clock constraints for FIFO_WR_CLK for 900 MHz. Needed for FIFO_WR_CLK timing arcs
# create_clock -period 1.111 -name {banka_rxclk[0]} -waveform {0.000 0.556} [get_ports {banka_rxclk[0]}]
# create_clock -period 1.111 -name {bankb_rxclk[0]} -waveform {0.000 0.556} [get_ports {bankb_rxclk[0]}]
# create_clock -period 1.111 -name {bankc_rxclk[0]} -waveform {0.000 0.556} [get_ports {bankc_rxclk[0]}]
# create_clock -period 1.111 -name {bankd_rxclk[0]} -waveform {0.000 0.556} [get_ports {bankd_rxclk[0]}]
# create_clock -period 1.111 -name {banke_rxclk[0]} -waveform {0.000 0.556} [get_ports {banke_rxclk[0]}]
# create_clock -period 1.111 -name {bankf_rxclk[0]} -waveform {0.000 0.555} [get_ports {bankf_rxclk[0]}]

#Capture clock constraints for FIFO_WR_CLK for 900 MHz. Needed for FIFO_WR_CLK timing arcs
# create_clock -period 0.625 -name {banka_rxclk[0]} -waveform {0.000 0.3125} [get_ports {banka_rxclk[0]}]
# create_clock -period 0.625 -name {bankb_rxclk[0]} -waveform {0.000 0.3125} [get_ports {bankb_rxclk[0]}]
# create_clock -period 0.625 -name {bankc_rxclk[0]} -waveform {0.000 0.3125} [get_ports {bankc_rxclk[0]}]
# create_clock -period 0.625 -name {bankd_rxclk[0]} -waveform {0.000 0.3125} [get_ports {bankd_rxclk[0]}]
# create_clock -period 0.625 -name {banke_rxclk[0]} -waveform {0.000 0.3125} [get_ports {banke_rxclk[0]}]
# create_clock -period 0.625 -name {bankf_rxclk[0]} -waveform {0.000 0.3125} [get_ports {bankf_rxclk[0]}]

#Capture clock constraints for FIFO_WR_CLK for 1447 MHz. Needed for FIFO_WR_CLK timing arcs
#2694 Mbps for 1mp > 1347 MHz strobe/DQS
# 742 ps period which should give fifo_wr_clk period of 2.764 ns
 create_clock -period 0.742 -name {banka_rxclk[0]} -waveform {0.000 0.371} [get_ports {banka_rxclk[0]}]
 create_clock -period 0.742 -name {bankb_rxclk[0]} -waveform {0.000 0.371} [get_ports {bankb_rxclk[0]}]
 create_clock -period 0.742 -name {bankc_rxclk[0]} -waveform {0.000 0.371} [get_ports {bankc_rxclk[0]}]
 create_clock -period 0.742 -name {bankd_rxclk[0]} -waveform {0.000 0.371} [get_ports {bankd_rxclk[0]}]
 create_clock -period 0.742 -name {banke_rxclk[0]} -waveform {0.000 0.371} [get_ports {banke_rxclk[0]}]
 create_clock -period 0.742 -name {bankf_rxclk[0]} -waveform {0.000 0.371} [get_ports {bankf_rxclk[0]}]

# Use the CLOCK_LOW_FANOUT to guide the clock roots to a vertically adjacent to the I/O banks
set_property CLOCK_LOW_FANOUT 1 [get_nets banka_pll_clkout0]
set_property CLOCK_LOW_FANOUT 1 [get_nets bankb_pll_clkout0]
set_property CLOCK_LOW_FANOUT 1 [get_nets bankc_pll_clkout0]
set_property CLOCK_LOW_FANOUT 1 [get_nets bankd_pll_clkout0]
set_property CLOCK_LOW_FANOUT 1 [get_nets banke_pll_clkout0]
set_property CLOCK_LOW_FANOUT 1 [get_nets bankf_pll_clkout0]


####################################################################################
# Pin constraints
####################################################################################

set_property PACKAGE_PIN CT61 [get_ports clk]
set_property IOSTANDARD DIFF_POD12 [get_ports clk]


set_property IOSTANDARD POD12 [get_ports {bank?_data_pins[*]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bank?_rxclk*[*]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {banka_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {banka_wrclk_n[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankb_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankb_wrclk_n[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankc_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankc_wrclk_n[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankd_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankd_wrclk_n[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {banke_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {banke_wrclk_n[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankf_wrclk[0]}]
set_property IOSTANDARD DIFF_POD12 [get_ports {bankf_wrclk_n[0]}]
set_property ODT RTT_60 [get_ports {bank*_rxclk[*]}]
set_property ODT RTT_60 [get_ports {bank*_data_pins[*]}]

set_property SLEW FAST [get_ports {banka_data_pins[*]}]
set_property SLEW FAST [get_ports {bankb_data_pins[*]}]
set_property SLEW FAST [get_ports {bankc_data_pins[*]}]
set_property SLEW FAST [get_ports {bankd_data_pins[*]}]
set_property SLEW FAST [get_ports {banke_data_pins[*]}]
set_property SLEW FAST [get_ports {bankf_data_pins[*]}]
set_property SLEW FAST [get_ports {banka_wrclk[0]}]
set_property SLEW FAST [get_ports {banka_wrclk_n[0]}]
set_property SLEW FAST [get_ports {bankb_wrclk[0]}]
set_property SLEW FAST [get_ports {bankb_wrclk_n[0]}]
set_property SLEW FAST [get_ports {bankc_wrclk[0]}]
set_property SLEW FAST [get_ports {bankc_wrclk_n[0]}]
set_property SLEW FAST [get_ports {bankd_wrclk[0]}]
set_property SLEW FAST [get_ports {bankd_wrclk_n[0]}]
set_property SLEW FAST [get_ports {banke_wrclk[0]}]
set_property SLEW FAST [get_ports {banke_wrclk_n[0]}]
set_property SLEW FAST [get_ports {bankf_wrclk[0]}]
set_property SLEW FAST [get_ports {bankf_wrclk_n[0]}]





# Setting false path for a status signal that doesn't need to be timed.
set_false_path  -to [get_pins bank*_intf_rdy_reg_reg/D]
# Setting false path to the VIO block as this is for simulation purposes
set_false_path -from [get_pins {genblk1[*].inst_bank*_prbs_checker/DATA_OUT_reg[*]/C}]
set_false_path -from [get_pins bank*_intf_rdy_reg_reg/C] -to [get_pins bank*_int_test_startchk_reg/D]
set_false_path -from [get_pins bank*_intf_rdy_reg_reg/C] -to [get_pins bank*_prbs_chk_rst*/D]
set_false_path -from [get_pins bankf_intf_rdy_reg_reg/C] -to [get_pins bankf_prbs_chk_rst_reg/D]



set_property PACKAGE_PIN CT44 [get_ports {bankf_data_pins[0]}]
set_property PACKAGE_PIN DA45 [get_ports {bankf_data_pins[10]}]
set_property PACKAGE_PIN DA44 [get_ports {bankf_data_pins[11]}]
set_property PACKAGE_PIN DB44 [get_ports {bankf_data_pins[12]}]
set_property PACKAGE_PIN DB43 [get_ports {bankf_data_pins[13]}]
set_property PACKAGE_PIN DB47 [get_ports {bankf_data_pins[14]}]
set_property PACKAGE_PIN DB46 [get_ports {bankf_data_pins[15]}]
set_property PACKAGE_PIN DC47 [get_ports {bankf_data_pins[16]}]
set_property PACKAGE_PIN DC46 [get_ports {bankf_data_pins[17]}]
set_property PACKAGE_PIN DC45 [get_ports {bankf_data_pins[18]}]
set_property PACKAGE_PIN DC44 [get_ports {bankf_data_pins[19]}]
set_property PACKAGE_PIN CU44 [get_ports {bankf_data_pins[1]}]
set_property PACKAGE_PIN CG47 [get_ports {bankf_data_pins[20]}]
set_property PACKAGE_PIN CH47 [get_ports {bankf_data_pins[21]}]
set_property PACKAGE_PIN CH46 [get_ports {bankf_data_pins[22]}]
set_property PACKAGE_PIN CH45 [get_ports {bankf_data_pins[23]}]
set_property PACKAGE_PIN CJ45 [get_ports {bankf_data_pins[24]}]
set_property PACKAGE_PIN CJ44 [get_ports {bankf_data_pins[25]}]
set_property PACKAGE_PIN CJ47 [get_ports {bankf_data_pins[26]}]
set_property PACKAGE_PIN CK46 [get_ports {bankf_data_pins[27]}]
set_property PACKAGE_PIN CK45 [get_ports {bankf_data_pins[28]}]
set_property PACKAGE_PIN CL45 [get_ports {bankf_data_pins[29]}]
set_property PACKAGE_PIN CV45 [get_ports {bankf_data_pins[2]}]
set_property PACKAGE_PIN CL46 [get_ports {bankf_data_pins[30]}]
set_property PACKAGE_PIN CM46 [get_ports {bankf_data_pins[31]}]
set_property PACKAGE_PIN CD45 [get_ports {bankf_data_pins[32]}]
set_property PACKAGE_PIN CD44 [get_ports {bankf_data_pins[33]}]
set_property PACKAGE_PIN CD47 [get_ports {bankf_data_pins[34]}]
set_property PACKAGE_PIN CE47 [get_ports {bankf_data_pins[35]}]
set_property PACKAGE_PIN CE46 [get_ports {bankf_data_pins[36]}]
set_property PACKAGE_PIN CE45 [get_ports {bankf_data_pins[37]}]
set_property PACKAGE_PIN CF45 [get_ports {bankf_data_pins[38]}]
set_property PACKAGE_PIN CF44 [get_ports {bankf_data_pins[39]}]
set_property PACKAGE_PIN CV44 [get_ports {bankf_data_pins[3]}]
set_property PACKAGE_PIN CF46 [get_ports {bankf_data_pins[40]}]
set_property PACKAGE_PIN CG46 [get_ports {bankf_data_pins[41]}]
set_property PACKAGE_PIN CG44 [get_ports {bankf_data_pins[42]}]
set_property PACKAGE_PIN CH44 [get_ports {bankf_data_pins[43]}]
set_property PACKAGE_PIN CM44 [get_ports {bankf_data_pins[44]}]
set_property PACKAGE_PIN CN44 [get_ports {bankf_data_pins[45]}]
set_property PACKAGE_PIN CN46 [get_ports {bankf_data_pins[46]}]
set_property PACKAGE_PIN CN45 [get_ports {bankf_data_pins[47]}]
set_property PACKAGE_PIN CV46 [get_ports {bankf_data_pins[4]}]
set_property PACKAGE_PIN CW45 [get_ports {bankf_data_pins[5]}]
set_property PACKAGE_PIN CW44 [get_ports {bankf_data_pins[6]}]
set_property PACKAGE_PIN CY45 [get_ports {bankf_data_pins[7]}]
set_property PACKAGE_PIN CY46 [get_ports {bankf_data_pins[8]}]
set_property PACKAGE_PIN DA46 [get_ports {bankf_data_pins[9]}]
set_property PACKAGE_PIN CR45 [get_ports {bankf_rxclk[0]}]
set_property PACKAGE_PIN CT45 [get_ports {bankf_rxclk_n[0]}]
set_property PACKAGE_PIN CP45 [get_ports {bankf_wrclk[0]}]


set_property PACKAGE_PIN CU38 [get_ports {banke_data_pins[0]}]
set_property PACKAGE_PIN CY38 [get_ports {banke_data_pins[10]}]
set_property PACKAGE_PIN DA38 [get_ports {banke_data_pins[11]}]
set_property PACKAGE_PIN DA39 [get_ports {banke_data_pins[12]}]
set_property PACKAGE_PIN DB39 [get_ports {banke_data_pins[13]}]
set_property PACKAGE_PIN DA36 [get_ports {banke_data_pins[14]}]
set_property PACKAGE_PIN DB36 [get_ports {banke_data_pins[15]}]
set_property PACKAGE_PIN DB37 [get_ports {banke_data_pins[16]}]
set_property PACKAGE_PIN DC37 [get_ports {banke_data_pins[17]}]
set_property PACKAGE_PIN DB38 [get_ports {banke_data_pins[18]}]
set_property PACKAGE_PIN DC39 [get_ports {banke_data_pins[19]}]
set_property PACKAGE_PIN CU37 [get_ports {banke_data_pins[1]}]
set_property PACKAGE_PIN CH39 [get_ports {banke_data_pins[20]}]
set_property PACKAGE_PIN CJ39 [get_ports {banke_data_pins[21]}]
set_property PACKAGE_PIN CJ38 [get_ports {banke_data_pins[22]}]
set_property PACKAGE_PIN CK37 [get_ports {banke_data_pins[23]}]
set_property PACKAGE_PIN CK40 [get_ports {banke_data_pins[24]}]
set_property PACKAGE_PIN CL40 [get_ports {banke_data_pins[25]}]
set_property PACKAGE_PIN CM39 [get_ports {banke_data_pins[26]}]
set_property PACKAGE_PIN CN39 [get_ports {banke_data_pins[27]}]
set_property PACKAGE_PIN CM38 [get_ports {banke_data_pins[28]}]
set_property PACKAGE_PIN CM37 [get_ports {banke_data_pins[29]}]
set_property PACKAGE_PIN CV37 [get_ports {banke_data_pins[2]}]
set_property PACKAGE_PIN CN37 [get_ports {banke_data_pins[30]}]
set_property PACKAGE_PIN CP37 [get_ports {banke_data_pins[31]}]
set_property PACKAGE_PIN CD38 [get_ports {banke_data_pins[32]}]
set_property PACKAGE_PIN CD37 [get_ports {banke_data_pins[33]}]
set_property PACKAGE_PIN CD39 [get_ports {banke_data_pins[34]}]
set_property PACKAGE_PIN CE38 [get_ports {banke_data_pins[35]}]
set_property PACKAGE_PIN CE37 [get_ports {banke_data_pins[36]}]
set_property PACKAGE_PIN CF38 [get_ports {banke_data_pins[37]}]
set_property PACKAGE_PIN CF39 [get_ports {banke_data_pins[38]}]
set_property PACKAGE_PIN CG39 [get_ports {banke_data_pins[39]}]
set_property PACKAGE_PIN CV36 [get_ports {banke_data_pins[3]}]
set_property PACKAGE_PIN CG38 [get_ports {banke_data_pins[40]}]
set_property PACKAGE_PIN CG37 [get_ports {banke_data_pins[41]}]
set_property PACKAGE_PIN CH37 [get_ports {banke_data_pins[42]}]
set_property PACKAGE_PIN CJ37 [get_ports {banke_data_pins[43]}]
set_property PACKAGE_PIN CN40 [get_ports {banke_data_pins[44]}]
set_property PACKAGE_PIN CP39 [get_ports {banke_data_pins[45]}]
set_property PACKAGE_PIN CP38 [get_ports {banke_data_pins[46]}]
set_property PACKAGE_PIN CR38 [get_ports {banke_data_pins[47]}]
set_property PACKAGE_PIN CV39 [get_ports {banke_data_pins[4]}]
set_property PACKAGE_PIN CW39 [get_ports {banke_data_pins[5]}]
set_property PACKAGE_PIN CW38 [get_ports {banke_data_pins[6]}]
set_property PACKAGE_PIN CW37 [get_ports {banke_data_pins[7]}]
set_property PACKAGE_PIN CY37 [get_ports {banke_data_pins[8]}]
set_property PACKAGE_PIN CY36 [get_ports {banke_data_pins[9]}]
set_property PACKAGE_PIN CT36 [get_ports {banke_rxclk[0]}]
set_property PACKAGE_PIN CU36 [get_ports {banke_rxclk_n[0]}]
set_property PACKAGE_PIN CR37 [get_ports {banke_wrclk[0]}]


set_property PACKAGE_PIN CV41 [get_ports {bankd_data_pins[0]}]
set_property PACKAGE_PIN CV42 [get_ports {bankd_data_pins[10]}]
set_property PACKAGE_PIN CW42 [get_ports {bankd_data_pins[11]}]
set_property PACKAGE_PIN CW43 [get_ports {bankd_data_pins[12]}]
set_property PACKAGE_PIN CY43 [get_ports {bankd_data_pins[13]}]
set_property PACKAGE_PIN CY42 [get_ports {bankd_data_pins[14]}]
set_property PACKAGE_PIN CY41 [get_ports {bankd_data_pins[15]}]
set_property PACKAGE_PIN DA43 [get_ports {bankd_data_pins[16]}]
set_property PACKAGE_PIN DB42 [get_ports {bankd_data_pins[17]}]
set_property PACKAGE_PIN DB41 [get_ports {bankd_data_pins[18]}]
set_property PACKAGE_PIN DC42 [get_ports {bankd_data_pins[19]}]
set_property PACKAGE_PIN CV40 [get_ports {bankd_data_pins[1]}]
set_property PACKAGE_PIN CD42 [get_ports {bankd_data_pins[20]}]
set_property PACKAGE_PIN CE42 [get_ports {bankd_data_pins[21]}]
set_property PACKAGE_PIN CE43 [get_ports {bankd_data_pins[22]}]
set_property PACKAGE_PIN CF43 [get_ports {bankd_data_pins[23]}]
set_property PACKAGE_PIN CG43 [get_ports {bankd_data_pins[24]}]
set_property PACKAGE_PIN CG42 [get_ports {bankd_data_pins[25]}]
set_property PACKAGE_PIN CH42 [get_ports {bankd_data_pins[26]}]
set_property PACKAGE_PIN CJ42 [get_ports {bankd_data_pins[27]}]
set_property PACKAGE_PIN CJ43 [get_ports {bankd_data_pins[28]}]
set_property PACKAGE_PIN CK42 [get_ports {bankd_data_pins[29]}]
set_property PACKAGE_PIN CW40 [get_ports {bankd_data_pins[2]}]
set_property PACKAGE_PIN CM43 [get_ports {bankd_data_pins[30]}]
set_property PACKAGE_PIN CM42 [get_ports {bankd_data_pins[31]}]
set_property PACKAGE_PIN CD40 [get_ports {bankd_data_pins[32]}]
set_property PACKAGE_PIN CE40 [get_ports {bankd_data_pins[33]}]
set_property PACKAGE_PIN CE41 [get_ports {bankd_data_pins[34]}]
set_property PACKAGE_PIN CF41 [get_ports {bankd_data_pins[35]}]
set_property PACKAGE_PIN CF40 [get_ports {bankd_data_pins[36]}]
set_property PACKAGE_PIN CG41 [get_ports {bankd_data_pins[37]}]
set_property PACKAGE_PIN CH41 [get_ports {bankd_data_pins[38]}]
set_property PACKAGE_PIN CH40 [get_ports {bankd_data_pins[39]}]
set_property PACKAGE_PIN CY40 [get_ports {bankd_data_pins[3]}]
set_property PACKAGE_PIN CJ40 [get_ports {bankd_data_pins[40]}]
set_property PACKAGE_PIN CK41 [get_ports {bankd_data_pins[41]}]
set_property PACKAGE_PIN CL41 [get_ports {bankd_data_pins[42]}]
set_property PACKAGE_PIN CM41 [get_ports {bankd_data_pins[43]}]
set_property PACKAGE_PIN CN42 [get_ports {bankd_data_pins[44]}]
set_property PACKAGE_PIN CN41 [get_ports {bankd_data_pins[45]}]
set_property PACKAGE_PIN CP43 [get_ports {bankd_data_pins[46]}]
set_property PACKAGE_PIN CP42 [get_ports {bankd_data_pins[47]}]
set_property PACKAGE_PIN DA41 [get_ports {bankd_data_pins[4]}]
set_property PACKAGE_PIN DA40 [get_ports {bankd_data_pins[5]}]
set_property PACKAGE_PIN DC41 [get_ports {bankd_data_pins[6]}]
set_property PACKAGE_PIN DC40 [get_ports {bankd_data_pins[7]}]
set_property PACKAGE_PIN CT43 [get_ports {bankd_data_pins[8]}]
set_property PACKAGE_PIN CU43 [get_ports {bankd_data_pins[9]}]
set_property PACKAGE_PIN CT41 [get_ports {bankd_rxclk[0]}]
set_property PACKAGE_PIN CT40 [get_ports {bankd_rxclk_n[0]}]
set_property PACKAGE_PIN CR43 [get_ports {bankd_wrclk[0]}]


set_property PACKAGE_PIN CT56 [get_ports {bankc_data_pins[0]}]
set_property PACKAGE_PIN CY57 [get_ports {bankc_data_pins[10]}]
set_property PACKAGE_PIN DA56 [get_ports {bankc_data_pins[11]}]
set_property PACKAGE_PIN DA55 [get_ports {bankc_data_pins[12]}]
set_property PACKAGE_PIN DB56 [get_ports {bankc_data_pins[13]}]
set_property PACKAGE_PIN DB54 [get_ports {bankc_data_pins[14]}]
set_property PACKAGE_PIN DC54 [get_ports {bankc_data_pins[15]}]
set_property PACKAGE_PIN DB57 [get_ports {bankc_data_pins[16]}]
set_property PACKAGE_PIN DC57 [get_ports {bankc_data_pins[17]}]
set_property PACKAGE_PIN DC56 [get_ports {bankc_data_pins[18]}]
set_property PACKAGE_PIN DC55 [get_ports {bankc_data_pins[19]}]
set_property PACKAGE_PIN CT55 [get_ports {bankc_data_pins[1]}]
set_property PACKAGE_PIN CG58 [get_ports {bankc_data_pins[20]}]
set_property PACKAGE_PIN CH57 [get_ports {bankc_data_pins[21]}]
set_property PACKAGE_PIN CH56 [get_ports {bankc_data_pins[22]}]
set_property PACKAGE_PIN CH55 [get_ports {bankc_data_pins[23]}]
set_property PACKAGE_PIN CJ55 [get_ports {bankc_data_pins[24]}]
set_property PACKAGE_PIN CK55 [get_ports {bankc_data_pins[25]}]
set_property PACKAGE_PIN CJ57 [get_ports {bankc_data_pins[26]}]
set_property PACKAGE_PIN CK56 [get_ports {bankc_data_pins[27]}]
set_property PACKAGE_PIN CL56 [get_ports {bankc_data_pins[28]}]
set_property PACKAGE_PIN CL55 [get_ports {bankc_data_pins[29]}]
set_property PACKAGE_PIN CU56 [get_ports {bankc_data_pins[2]}]
set_property PACKAGE_PIN CM57 [get_ports {bankc_data_pins[30]}]
set_property PACKAGE_PIN CM56 [get_ports {bankc_data_pins[31]}]
set_property PACKAGE_PIN CD55 [get_ports {bankc_data_pins[32]}]
set_property PACKAGE_PIN CE55 [get_ports {bankc_data_pins[33]}]
set_property PACKAGE_PIN CD58 [get_ports {bankc_data_pins[34]}]
set_property PACKAGE_PIN CD57 [get_ports {bankc_data_pins[35]}]
set_property PACKAGE_PIN CE58 [get_ports {bankc_data_pins[36]}]
set_property PACKAGE_PIN CF58 [get_ports {bankc_data_pins[37]}]
set_property PACKAGE_PIN CE57 [get_ports {bankc_data_pins[38]}]
set_property PACKAGE_PIN CE56 [get_ports {bankc_data_pins[39]}]
set_property PACKAGE_PIN CV56 [get_ports {bankc_data_pins[3]}]
set_property PACKAGE_PIN CF56 [get_ports {bankc_data_pins[40]}]
set_property PACKAGE_PIN CF55 [get_ports {bankc_data_pins[41]}]
set_property PACKAGE_PIN CG57 [get_ports {bankc_data_pins[42]}]
set_property PACKAGE_PIN CG56 [get_ports {bankc_data_pins[43]}]
set_property PACKAGE_PIN CM58 [get_ports {bankc_data_pins[44]}]
set_property PACKAGE_PIN CN57 [get_ports {bankc_data_pins[45]}]
set_property PACKAGE_PIN CN56 [get_ports {bankc_data_pins[46]}]
set_property PACKAGE_PIN CN55 [get_ports {bankc_data_pins[47]}]
set_property PACKAGE_PIN CV57 [get_ports {bankc_data_pins[4]}]
set_property PACKAGE_PIN CW57 [get_ports {bankc_data_pins[5]}]
set_property PACKAGE_PIN CV55 [get_ports {bankc_data_pins[6]}]
set_property PACKAGE_PIN CW55 [get_ports {bankc_data_pins[7]}]
set_property PACKAGE_PIN CY56 [get_ports {bankc_data_pins[8]}]
set_property PACKAGE_PIN CY55 [get_ports {bankc_data_pins[9]}]
set_property PACKAGE_PIN CR58 [get_ports {bankc_rxclk[0]}]
set_property PACKAGE_PIN CR57 [get_ports {bankc_rxclk_n[0]}]
set_property PACKAGE_PIN CP58 [get_ports {bankc_wrclk[0]}]


set_property PACKAGE_PIN CV62 [get_ports {bankb_data_pins[0]}]
set_property PACKAGE_PIN CW65 [get_ports {bankb_data_pins[10]}]
set_property PACKAGE_PIN CY65 [get_ports {bankb_data_pins[11]}]
set_property PACKAGE_PIN DA64 [get_ports {bankb_data_pins[12]}]
set_property PACKAGE_PIN DA63 [get_ports {bankb_data_pins[13]}]
set_property PACKAGE_PIN DA65 [get_ports {bankb_data_pins[14]}]
set_property PACKAGE_PIN DB64 [get_ports {bankb_data_pins[15]}]
set_property PACKAGE_PIN DB63 [get_ports {bankb_data_pins[16]}]
set_property PACKAGE_PIN DC64 [get_ports {bankb_data_pins[17]}]
set_property PACKAGE_PIN DC66 [get_ports {bankb_data_pins[18]}]
set_property PACKAGE_PIN DC65 [get_ports {bankb_data_pins[19]}]
set_property PACKAGE_PIN CW62 [get_ports {bankb_data_pins[1]}]
set_property PACKAGE_PIN CD65 [get_ports {bankb_data_pins[20]}]
set_property PACKAGE_PIN CE65 [get_ports {bankb_data_pins[21]}]
set_property PACKAGE_PIN CF65 [get_ports {bankb_data_pins[22]}]
set_property PACKAGE_PIN CG64 [get_ports {bankb_data_pins[23]}]
set_property PACKAGE_PIN CH65 [get_ports {bankb_data_pins[24]}]
set_property PACKAGE_PIN CH64 [get_ports {bankb_data_pins[25]}]
set_property PACKAGE_PIN CJ65 [get_ports {bankb_data_pins[26]}]
set_property PACKAGE_PIN CK65 [get_ports {bankb_data_pins[27]}]
set_property PACKAGE_PIN CK63 [get_ports {bankb_data_pins[28]}]
set_property PACKAGE_PIN CL63 [get_ports {bankb_data_pins[29]}]
set_property PACKAGE_PIN CW64 [get_ports {bankb_data_pins[2]}]
set_property PACKAGE_PIN CL64 [get_ports {bankb_data_pins[30]}]
set_property PACKAGE_PIN CM64 [get_ports {bankb_data_pins[31]}]
set_property PACKAGE_PIN CD63 [get_ports {bankb_data_pins[32]}]
set_property PACKAGE_PIN CD62 [get_ports {bankb_data_pins[33]}]
set_property PACKAGE_PIN CE63 [get_ports {bankb_data_pins[34]}]
set_property PACKAGE_PIN CE62 [get_ports {bankb_data_pins[35]}]
set_property PACKAGE_PIN CF64 [get_ports {bankb_data_pins[36]}]
set_property PACKAGE_PIN CF63 [get_ports {bankb_data_pins[37]}]
set_property PACKAGE_PIN CG63 [get_ports {bankb_data_pins[38]}]
set_property PACKAGE_PIN CG62 [get_ports {bankb_data_pins[39]}]
set_property PACKAGE_PIN CW63 [get_ports {bankb_data_pins[3]}]
set_property PACKAGE_PIN CH62 [get_ports {bankb_data_pins[40]}]
set_property PACKAGE_PIN CJ62 [get_ports {bankb_data_pins[41]}]
set_property PACKAGE_PIN CJ64 [get_ports {bankb_data_pins[42]}]
set_property PACKAGE_PIN CJ63 [get_ports {bankb_data_pins[43]}]
set_property PACKAGE_PIN CM63 [get_ports {bankb_data_pins[44]}]
set_property PACKAGE_PIN CN64 [get_ports {bankb_data_pins[45]}]
set_property PACKAGE_PIN CN65 [get_ports {bankb_data_pins[46]}]
set_property PACKAGE_PIN CP65 [get_ports {bankb_data_pins[47]}]
set_property PACKAGE_PIN CY63 [get_ports {bankb_data_pins[4]}]
set_property PACKAGE_PIN CY62 [get_ports {bankb_data_pins[5]}]
set_property PACKAGE_PIN DB62 [get_ports {bankb_data_pins[6]}]
set_property PACKAGE_PIN DC62 [get_ports {bankb_data_pins[7]}]
set_property PACKAGE_PIN CV65 [get_ports {bankb_data_pins[8]}]
set_property PACKAGE_PIN CV64 [get_ports {bankb_data_pins[9]}]
set_property PACKAGE_PIN CT64 [get_ports {bankb_rxclk[0]}]
set_property PACKAGE_PIN CT63 [get_ports {bankb_rxclk_n[0]}]
set_property PACKAGE_PIN CR65 [get_ports {bankb_wrclk[0]}]


set_property PACKAGE_PIN CT69 [get_ports {banka_data_pins[0]}]
set_property PACKAGE_PIN CW67 [get_ports {banka_data_pins[10]}]
set_property PACKAGE_PIN CY67 [get_ports {banka_data_pins[11]}]
set_property PACKAGE_PIN CY66 [get_ports {banka_data_pins[12]}]
set_property PACKAGE_PIN DA66 [get_ports {banka_data_pins[13]}]
set_property PACKAGE_PIN CY68 [get_ports {banka_data_pins[14]}]
set_property PACKAGE_PIN DA68 [get_ports {banka_data_pins[15]}]
set_property PACKAGE_PIN DB68 [get_ports {banka_data_pins[16]}]
set_property PACKAGE_PIN DC67 [get_ports {banka_data_pins[17]}]
set_property PACKAGE_PIN DB67 [get_ports {banka_data_pins[18]}]
set_property PACKAGE_PIN DB66 [get_ports {banka_data_pins[19]}]
set_property PACKAGE_PIN CU69 [get_ports {banka_data_pins[1]}]
set_property PACKAGE_PIN CH67 [get_ports {banka_data_pins[20]}]
set_property PACKAGE_PIN CH66 [get_ports {banka_data_pins[21]}]
set_property PACKAGE_PIN CJ69 [get_ports {banka_data_pins[22]}]
set_property PACKAGE_PIN CK68 [get_ports {banka_data_pins[23]}]
set_property PACKAGE_PIN CJ68 [get_ports {banka_data_pins[24]}]
set_property PACKAGE_PIN CJ67 [get_ports {banka_data_pins[25]}]
set_property PACKAGE_PIN CK67 [get_ports {banka_data_pins[26]}]
set_property PACKAGE_PIN CL68 [get_ports {banka_data_pins[27]}]
set_property PACKAGE_PIN CM69 [get_ports {banka_data_pins[28]}]
set_property PACKAGE_PIN CM68 [get_ports {banka_data_pins[29]}]
set_property PACKAGE_PIN CT66 [get_ports {banka_data_pins[2]}]
set_property PACKAGE_PIN CM67 [get_ports {banka_data_pins[30]}]
set_property PACKAGE_PIN CM66 [get_ports {banka_data_pins[31]}]
set_property PACKAGE_PIN CD66 [get_ports {banka_data_pins[32]}]
set_property PACKAGE_PIN CE66 [get_ports {banka_data_pins[33]}]
set_property PACKAGE_PIN CE68 [get_ports {banka_data_pins[34]}]
set_property PACKAGE_PIN CE67 [get_ports {banka_data_pins[35]}]
set_property PACKAGE_PIN CF66 [get_ports {banka_data_pins[36]}]
set_property PACKAGE_PIN CG66 [get_ports {banka_data_pins[37]}]
set_property PACKAGE_PIN CF69 [get_ports {banka_data_pins[38]}]
set_property PACKAGE_PIN CF68 [get_ports {banka_data_pins[39]}]
set_property PACKAGE_PIN CU66 [get_ports {banka_data_pins[3]}]
set_property PACKAGE_PIN CG69 [get_ports {banka_data_pins[40]}]
set_property PACKAGE_PIN CH69 [get_ports {banka_data_pins[41]}]
set_property PACKAGE_PIN CG68 [get_ports {banka_data_pins[42]}]
set_property PACKAGE_PIN CG67 [get_ports {banka_data_pins[43]}]
set_property PACKAGE_PIN CN67 [get_ports {banka_data_pins[44]}]
set_property PACKAGE_PIN CN66 [get_ports {banka_data_pins[45]}]
set_property PACKAGE_PIN CN69 [get_ports {banka_data_pins[46]}]
set_property PACKAGE_PIN CP69 [get_ports {banka_data_pins[47]}]
set_property PACKAGE_PIN CU68 [get_ports {banka_data_pins[4]}]
set_property PACKAGE_PIN CU67 [get_ports {banka_data_pins[5]}]
set_property PACKAGE_PIN CV67 [get_ports {banka_data_pins[6]}]
set_property PACKAGE_PIN CV66 [get_ports {banka_data_pins[7]}]
set_property PACKAGE_PIN CV69 [get_ports {banka_data_pins[8]}]
set_property PACKAGE_PIN CW68 [get_ports {banka_data_pins[9]}]
set_property PACKAGE_PIN CR67 [get_ports {banka_rxclk[0]}]
set_property PACKAGE_PIN CR66 [get_ports {banka_rxclk_n[0]}]
set_property PACKAGE_PIN CP68 [get_ports {banka_wrclk[0]}]

